1. Field of the Invention
The invention relates to thin film transistor substrates, methods of manufacturing thin film transistor substrates, and liquid crystal display panels including thin film transistor substrates. More particularly, the invention relates to a thin film transistor substrate having a structure in which a common electrode is disposed on a gate insulating layer and is connected to a common voltage line through a contact hole, as well as a method of manufacturing such a thin film transistor substrate and a PLS (plane-to-line switching) mode liquid crystal display panel including such a thin film transistor substrate.
2. Discussion of the Background
In order to improve the viewing angle of a liquid crystal display panel, different wide viewing angle technologies, such as in-plane switching (IPS) mode, fringe-field switching (FFS) mode, and patterned vertical alignment (PVA) mode, have been developed.
However, the above wide angle viewing technologies present challenges. For example, a field distortion in the upper part of an electrode may be caused due to a mode characteristic that uses a lateral field of the electrode, thereby causing the region that actually transmits backlight to be limited.
Therefore, recently, a plane-to-line switching (PLS) mode that utilizes the dead space of the electrode as an opening has been developed.
In PLS mode, a plane-shaped common electrode and a linear pixel electrode are disposed on a thin film transistor substrate. Liquid crystal molecules are aligned by an electrical field generated when voltages are applied to the electrodes. The PLS mode is advantageous because it removes the dead space of an electrode in IPS mode by using an additional common electrode.
In the PLS mode liquid crystal displays of the prior art a common electrode is formed first and then a gate line is formed. Thereafter, three layers, including a gate insulating layer, an active layer, and an ohmic contact layer, are sequentially deposited on the common electrode at a high temperature, for example, at 350° C. or higher.
In this case, if the common electrode, for example, an indium tin oxide (ITO), is exposed to a high temperature, the bonding strength between the compositions may weaken, and thus, the indium ion or the tin ion may damage the other layers. In order to prevent this damage, the three layers may be deposited at a lower temperature, for example, at 280° C. However, even if the weakening of the bonding strength between the compositions can be prevented, the interface properties of the three layers, including an active layer formed of amorphous silicon, is remarkably degraded, which may degrade the reliability of the thin film transistor.